Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual de usuario descargar pdf (Pagina 70)

FPGA Resource Consumption

III-58 Slave Controller – IP Core for Xilinx FPGAs

The EtherCAT IP core resource consumption figures for typical EtherCAT devices are based on

EtherCAT IP Core for Xilinx FPGAs Version 3.00c, Xilinx ISE 14.5, and Spartan-6 devices.

Table 17: EtherCAT IP Core resource consumption for typical EtherCAT Devices

EtherCAT Device

FMMU

DPRAM

[kByte]

PDI

Reg.

LUT6

32 Bit Digital I/O

4,800

5,800

Frequency Inverter

SPI

7,000

10,000

Encoder

SPI

9,900

13,200

Fieldbus Gateway

16 Bit µC

6,600

9,900

Servo Drive

16 Bit µC

9,400

13,200

NOTE: Register preset is standard. All devices have 2 MII ports including MII Management Interface, DC is 32 bit

wide (2 SyncSignals, 2 LatchSignals).

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual de usuario Pagina 70