Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual de usuario descargar pdf (Pagina 11)

FIGURES

Slave Controller – IP Core for Xilinx FPGAs III-XI

Figure 61: AXI Read Access ............................................................................................................... 125

Figure 62: AXI Write Access ................................................................................................................ 125

Figure 63: Distributed Clocks signals .................................................................................................. 126

Figure 64: LatchSignal timing .............................................................................................................. 126

Figure 65: SyncSignal timing ............................................................................................................... 126

Figure 66: I²C EEPROM signals .......................................................................................................... 127

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 143 144

Sin comentarios

Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual de usuario Pagina 11