Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual de usuario descargar pdf (Pagina 10)

FIGURES

III-X Slave Controller – IP Core for Xilinx FPGAs

FIGURES

Figure 1: EtherCAT IP Core Block Diagram ............................................................................................ 1

Figure 2: Frame Processing .................................................................................................................... 2

Figure 3: Design flow ............................................................................................................................. 10

Figure 4: Files installed with EtherCAT IP core setup ........................................................................... 23

Figure 5: IPCore_Config Open Menu .................................................................................................... 28

Figure 6: IP Core generation successful ............................................................................................... 28

Figure 7: EDK – Overview ..................................................................................................................... 30

Figure 8: EDK – Configuration of IP Core ............................................................................................. 30

Figure 9: EDK – Configuration Dialog ................................................................................................... 31

Figure 10: EDK – System Assembly View, Addresses tab ................................................................... 31

Figure 11: EDK – System Assembly View, Ports tab ............................................................................ 32

Figure 12: EtherCAT IP Core Configuration Interface ........................................................................... 34

Figure 13: Product ID tab ...................................................................................................................... 35

Figure 14: Physical Layer tab ................................................................................................................ 36

Figure 15: Internal Functions tab ........................................................................................................... 38

Figure 16: Feature Details tab ............................................................................................................... 40

Figure 17: Available PDI Interfaces ....................................................................................................... 42

Figure 18: Register Process Data Interface .......................................................................................... 43

Figure 19: Register PDI – Digital I/O Configuration............................................................................... 44

Figure 20: Register PDI – µC-Configuration.......................................................................................... 45

Figure 21: Register PDI – SPI Configuration ......................................................................................... 46

Figure 22: Register PDI – PLB Interface Configuration ........................................................................ 47

Figure 23: Register PDI – AXI4/AXI4 LITE Interface Configuration ...................................................... 48

Figure 24: EtherCAT IP Core clock source (MII) ................................................................................... 60

Figure 25: EtherCAT IP Core clock source (RMII) ................................................................................ 60

Figure 26: EtherCAT IP Core clock source (RGMII) ............................................................................. 60

Figure 27: PHY management Interface signals..................................................................................... 78

Figure 28: Example schematic with two individual MII management interfaces ................................... 79

Figure 29: MII Interface signals ............................................................................................................. 81

Figure 30: MII TX Timing Diagram ........................................................................................................ 82

Figure 31: MII timing RX signals............................................................................................................ 83

Figure 32: MII example schematic......................................................................................................... 84

Figure 33: RMII Interface signals........................................................................................................... 85

Figure 34: RMII example schematic ...................................................................................................... 86

Figure 35: RGMII Interface signals ........................................................................................................ 88

Figure 36: RGMII example schematic ................................................................................................... 89

Figure 37: IP core digital I/O signals ..................................................................................................... 92

Figure 38: Digital Output Principle Schematic ....................................................................................... 94

Figure 39: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 96

Figure 40: Digital Input: Input data sampled with LATCH_IN ................................................................ 96

Figure 41: Digital Input: Input data sampled with SYNC0/1 .................................................................. 96

Figure 42: Digital Output timing ............................................................................................................. 97

Figure 43: OUT_ENA timing .................................................................................................................. 97

Figure 44: SPI master and slave interconnection.................................................................................. 98

Figure 45: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .. 104

Figure 46: SPI read access (2 byte addressing, 1 byte read data) with Wait State byte .................... 105

Figure 47: SPI read access (2 byte addressing, 2 byte read data) with Wait State byte .................... 106

Figure 48: SPI write access (2 byte addressing, 1 byte write data) .................................................... 107

Figure 49: SPI write access (3 byte addressing, 1 byte write data) .................................................... 108

Figure 50: µController interconnection ................................................................................................ 109

Figure 51: Connection with 16 bit µControllers without byte addressing ............................................ 111

Figure 52: Connection with 8 bit µControllers (BHE and DATA[15:8] should not be left open) .......... 112

Figure 53: Read access (without preceding write access) .................................................................. 114

Figure 54: Write access (write after rising edge nWR, without preceding write access) .................... 115

Figure 55: Sequence of two write accesses and a read access ......................................................... 115

Figure 56: Write access (write after falling edge nWR) ....................................................................... 116

Figure 57: PLB signals ........................................................................................................................ 117

Figure 58: PLB Read Access .............................................................................................................. 120

Figure 59: PLB Write Access ............................................................................................................... 120

Figure 60: AXI4 signals ....................................................................................................................... 121

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manual de usuario Pagina 10

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