Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Manual de usuario Pagina 66
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Example Designs
III-54 Slave Controller – IP Core for Altera FPGAs
6.3 Altera Cyclone IV DE2-115 with NIOS and MII
6.3.1 Configuration and resource consumption
Table 15: Resource consumption NIOS example design DE2-115 MII
Configuration
Resources
EP4CE115
Physical layer
2x MII,
TX Shift, MIIM, Link state
and PHY configuration
through MI
Les
19,062
17 %
Internal Function
3x FMMU
4x SyncManager
1 KB RAM
Registers
9,039
8 %
Distributed clocks
32 bit,
2x Sync, 2x Latch
M9K
264
61 %
Feature details
AL Status Code register,
Extended Watchdog,
AL Event Mask register,
Watchdog counter, EPU
and PDI Error counter,
Lost Link Counter,
RUN_LED,
LED Test
PLLs
1
25 %
PDI
Avalon
32 bit
Multiplier
elements
0
0 %
6.3.2 Functionality
Configure ETHERNET0 and ETHERNET1 for MII mode by setting jumpers JP1 and JP2 to 2-3.
Master is connected to Port ETHERNET0 of DE2-115 (left side, next to VGA). Port ETHERNET1 (right
side) can be used to connect other EtherCAT slaves.
The NIOS demo application performs the following tasks:
Accept any EtherCAT Slave State request (copying AL Control to AL Status register)
Display EtherCAT IP Core version and slave state on LCD
RUN LED is LEDG8
Link/Activity LEDs are LEDG6 and LEDG7
LEDG0 – LEDG5 are showing a running light if the slave is in OPERATIONAL mode
Digital input data from the switches SW0-SW17 is available in the Process Data RAM
(0x1000:0x1003).
Digital input data from the push buttons KEY0-KEY3 is available in the Process Data RAM
(0x1004).
Digital output data from Digital Output register (0x1100:0x1103) is visualized with LEDR0-LEDR17
Digital output data from Digital Output register (0x1104:0x1107) is visualized with the 7-segment
LED displays
The NIOS demo application is not suitable for production, it cannot be certified. Use the EtherCAT
Slave Stack Code (SSC, available from the ETG) for products.
- ® FPGAs 1
- 1 Overview 13
- EtherCAT IP Core 14
- Table 4: Release notes 18
- Figure 3: Design flow 25
- 2 Features and Registers 28
- (0x0108:0x0109) 29
- Table 8: Legend 30
- IP Core 31
- V3.0.10 31
- Table 10: Legend 33
- 3 IP Core Installation 38
- Figure 5: License Setup 40
- 4 IP Core Usage 43
- 5 IP Core Configuration 44
- Figure 8: Documentation 45
- Figure 9: Product ID tab 46
- 09) is available if checked 51
- 6 Example Designs 61
- 7 FPGA Resource Consumption 69
- 8 IP Core Signals 71
- CLK25_2NS 72
- Table 20: SII EEPROM Signals 73
- Table 21: LED Signals 73
- PHY Management 75
- Table 24: PHY Interface MII 76
- Table 25: PHY Interface RMII 78
- Table 28: Digital I/O PDI 82
- Table 29: SPI PDI 83
- Table 30: 8/16 Bit µC PDI 83
- Table 31: 8 Bit µC PDI 83
- Table 32: 16 Bit µC PDI 84
- Table 33: Avalon PDI 84
- Table 34: AXI3 PDI 85
- 9 Ethernet Interface 86
- Ethernet PHY 87
- RX_D[3:0] 91
- 10 PDI Description 99
- Digital output pins 102
- LATCH_IN 104
- Figure 39: OUT_ENA timing 105
- Table 46: SPI signals 106
- Table 47: Address modes 107
- SPI_DO (MISO) 112
- SPI_DI (MOSI) 112
- SPI_CLK* 112
- SPI mode 1/3 SPI mode 0/2 113
- PDI Description 114
- 16 bit µController, async 119
- EtherCAT device 119
- 8 bit µController, async 120
- (with preceding write access) 122
- DATA0 DATA1 DATA2 DATA3 128
- ADR+1 ADR+3ADR+2 128
- Figure 57: AXI3 signals 129
- Table 59: AXI3 signals 129
- Figure 58: AXI Read Access 133
- Figure 59: AXI Write Access 133
- Output event time 134
- Table 63: I²C EEPROM signals 135
- Table 65: AC Characteristics 136
- Table 66: Forwarding Delays 136
- 14 Synthesis Constraints 137
- Synthesis Constraints 138
- Synthesis Constraints 139
- 15 Appendix 141
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