Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Manual de usuario Pagina 121
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PDI Description
Slave Controller – IP Core for Altera FPGAs III-109
10.3.9 Timing Specification
Table 56: µController timing characteristics IP Core
Parameter
Min
Max
Comment
PRELIMINARY TIMING
t
CS_to_BUSY
x
8
BUSY driven and valid after CS assertion
t
ADR_BHE_setup
x
8
ADR and BHE valid before RD assertion
t
RD_to_DATA_driven
0 ns
9
DATA bus driven after RD assertion
t
RD_to_BUSY
0 ns
9
x
8
BUSY asserted after RD assertion
t
read
External read time (RD assertion to BUSY
deassertion) with normal read busy output
(0x0152[0]). Additional 20 ns if delayed read
busy output is configured.
a) t
read_int
9
a) without preceding write access or
t
WR_to_RD
≥
t
write_int
or configuration: write after
falling edge of WR
b) t
read_int
+ t
write_int
-t
WR_to_RD
9
b) with preceding write access and
t
WR_to_RD
< t
write_int
c) 245 ns
9
c) 8 bit access, absolute worst case with
preceding write access (t
WR_to_RD
=min
,
t
write_int
=max)
d) 285 ns
9
d) 16 bit access, absolute worst case with
preceding write access (t
WR_to_RD
=min
,
t
write_int
=max)
t
read_int
a) 110 ns
9
b) 150 ns
9
a) 150 ns
9
b) 190 ns
9
Internal read time
a) 8 bit access
b) 16 bit access
t
BUSY_to_DATA_valid
a) x
8
-5 ns
b) x
8
-20 ns
DATA bus valid after device BUSY is
deasserted
a) normal read busy output
b) delayed read busy output
t
ADR_BHE_to_DATA_invalid
0 ns
9
DATA invalid after ADR or BHE change
t
CS_RD_to_DATA_release
0 ns
9
x
8
DATA bus released after CS deassertion or
RD deassertion
t
CS_to_BUSY_release
0 ns
9
x
8
BUSY released after CS deassertion
t
CS_delay
0 ns
9
Delay between CS deassertion an assertion
t
RD_delay
x
8
Delay between RD deassertion and
assertion
t
ADR_BHE_DATA_setup
x
8
ADR, BHE and Write DATA valid before WR
deassertion
t
ADR_BHE_DATA_hold
x
8
ADR, BHE and Write DATA valid after WR
deassertion
t
WR_active
x
8
WR assertion time
8
EtherCAT IP Core: time depends on synthesis results
9
EtherCAT IP Core: time depends on synthesis results, specified value has to be met anyway
- ® FPGAs 1
- 1 Overview 13
- EtherCAT IP Core 14
- Table 4: Release notes 18
- Figure 3: Design flow 25
- 2 Features and Registers 28
- (0x0108:0x0109) 29
- Table 8: Legend 30
- IP Core 31
- V3.0.10 31
- Table 10: Legend 33
- 3 IP Core Installation 38
- Figure 5: License Setup 40
- 4 IP Core Usage 43
- 5 IP Core Configuration 44
- Figure 8: Documentation 45
- Figure 9: Product ID tab 46
- 09) is available if checked 51
- 6 Example Designs 61
- 7 FPGA Resource Consumption 69
- 8 IP Core Signals 71
- CLK25_2NS 72
- Table 20: SII EEPROM Signals 73
- Table 21: LED Signals 73
- PHY Management 75
- Table 24: PHY Interface MII 76
- Table 25: PHY Interface RMII 78
- Table 28: Digital I/O PDI 82
- Table 29: SPI PDI 83
- Table 30: 8/16 Bit µC PDI 83
- Table 31: 8 Bit µC PDI 83
- Table 32: 16 Bit µC PDI 84
- Table 33: Avalon PDI 84
- Table 34: AXI3 PDI 85
- 9 Ethernet Interface 86
- Ethernet PHY 87
- RX_D[3:0] 91
- 10 PDI Description 99
- Digital output pins 102
- LATCH_IN 104
- Figure 39: OUT_ENA timing 105
- Table 46: SPI signals 106
- Table 47: Address modes 107
- SPI_DO (MISO) 112
- SPI_DI (MOSI) 112
- SPI_CLK* 112
- SPI mode 1/3 SPI mode 0/2 113
- PDI Description 114
- 16 bit µController, async 119
- EtherCAT device 119
- 8 bit µController, async 120
- (with preceding write access) 122
- DATA0 DATA1 DATA2 DATA3 128
- ADR+1 ADR+3ADR+2 128
- Figure 57: AXI3 signals 129
- Table 59: AXI3 signals 129
- Figure 58: AXI Read Access 133
- Figure 59: AXI Write Access 133
- Output event time 134
- Table 63: I²C EEPROM signals 135
- Table 65: AC Characteristics 136
- Table 66: Forwarding Delays 136
- 14 Synthesis Constraints 137
- Synthesis Constraints 138
- Synthesis Constraints 139
- 15 Appendix 141
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