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SII EEPROM
Slave Controller – Technology I-73
11.1 SII EEPROM Content
The ESC Configuration Area (EEPROM word addresses 0 to 7) is automatically read by the ESC after
power-on or reset. It contains the PDI configuration, DC settings, and the Configured Station Alias.
The consistency of the ESC Configuration data is secured with a checksum.
For SII coding refer to ETG.1000 EtherCAT Specification, Part 6, Clause 5.4, available in the
download area of the EtherCAT Technology Group website (http://www.ethercat.org).
The EtherCAT master can invoke reloading the EEPROM content. In this case the Configured Station
Alias register 0x0012:0x0013 and ESC Configuration register bits 0x0141[1,4,5,6,7] (enhanced link
detection) are not transferred into the registers, they are only transferred at the initial EEPROM
loading after power-on or reset.
The ESC Configuration Area is shown in Table 37.
Table 37: ESC Configuration Area
Word
Address
Parameter
Description
Register
Address
0x0
PDI Control/
ESC Configuration
Initialization value for PDI Control register
(EEPROM ADR 0x0000[9] is also mapped to
register 0x0110[2])
0x0140:0x0141
0x1
PDI Configuration
Initialization value for PDI Configuration
register
0x0150:0x0151
0x2
Pulse Length of
SYNC Signals
Initialization value for Pulse Length of SYNC
Signals register
0x0982:0x0983
0x3
Extended PDI
Configuration
Initialization value for extended PDI
Configuration register
0x0152:0x0153
0x4
Configured Station
Alias
Initialization value for Configured Station Alias
Address register
0x0012:0x0013
0x5
Reserved
Reserved, shall be zero
-
0x6
Reserved
Reserved, shall be zero
-
0x7
Checksum
Low byte contains remainder of division of
word 0 to word 6 as unsigned number divided
by the polynomial x
8
+x
2
+x+1(initial value
0xFF).
NOTE: For debugging purposes it is possible to
disable the checksum validation with a checksum
value of 0x88A4. Never use this for production!
-
NOTE: Reserved words or reserved bits of the ESC Configuration Area should be filled with 0.
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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