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Distributed Clocks

Slave Controller – Technology I-65

The registers used for LatchSignal event time stamping are shown in Table 34:

Table 34: Registers for Latch Input Events

Name

Description

0x0141[3:2]

ESC Configuration

Enable/Disable DC Units (power saving)

0x0151

Sync/Latch PDI Configuration

Configuration of SYNC/LATCH[1:0] pins

0x0980[5:4]

Cyclic Unit Control

Assignment of cyclic function to EtherCAT or

PDI

0x09A8

Latch0 Control

Latch unit configuration for Latch0

0x09A9

Latch1 Control

Latch unit configuration for Latch1

0x09AE

Latch0 Status

Latch status of Latch0

0x09AF

Latch1 Status

Latch status Latch1

0x09B0:0x09B7

Latch0 Time Positive Edge

System time at positive edge Latch0

0x09B8:0x09BF

Latch0 Time Negative Edge

System time at negative edge Latch0

0x09C0:0x09C7

Latch1 Time Positive Edge

System time at positive edge Latch1

0x09C8:0x09CF

Latch1 Time Negative Edge

System time at negative edge Latch1

0x09F0:0x09F3

EtherCAT Buffer Change

Event Time

Local time at beginning of frame causing

ECAT SyncManager buffer change event

0x09F8:0x09FB

PDI Buffer Start Event Time

Local time at PDI SyncManager buffer start

event

0x09FC:0x09FF

PDI Buffer Change Event

Time

Local time at PDI SyncManager buffer

change event

NOTE: Some of these registers are set via SII EEPROM/IP Core configuration, or they are not available in

specific ESCs. Refer to Section II for details.

9.2.4.1 Single Event Mode

In single event mode, only the timestamps of the first rising and the first falling edge of the

LatchSignals are recorded. The Latch Status registers (0x09AE:0x09AF) contain information about the

events which already have occurred. The Latch Time registers (0x09B0 to 0x09CF) contain the time

stamps.

Each event is acknowledged by reading the corresponding Latch Time register. After reading the

Latch Time register, the Latch unit is waiting for the next event. Latch events are mapped to the AL

Event Request register in single event mode.

9.2.4.2 Continuous Mode

In continuous mode, each event is stored in the Latch Time registers. At reading, the time stamp of the

last event is read. The Latch Status registers (0x09AE:0x09AF) do not reflect the latch event states in

continuous mode.

9.2.4.3 SyncManager Event

Some ESCs support debugging of SyncManager interactions with time stamps for buffer events. The

last event can be read out at the SyncManager Event Time registers (0x09F0:0x09FF), if the

SyncManager is configured appropriately.

9.2.5 ECAT or PDI Control

The SyncSignal unit and the two LatchSignal units of the Distributed Clocks entity can be assigned

independently by the master to be controlled either by ECAT or a local µController (PDI) using the

Cyclic Unit Control register 0x0980. With PDI control, a µController can e.g. set up cyclic interrupts for

itself.

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 115 116

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