
Features and Registers
Slave Controller – IP Core for Xilinx FPGAs III-17
V2.4.0-V2.4.4/
V2.04a-V2.04e
Register set
S M L
V2.3.0-V2.3.2/
V2.03a-V2.03d
Register set
S M L
V2.2.1/V2.2.0/
V2.02a
Register set
S M L
DC – Time Loop
Control Unit
DC – Receive Time
Latch mode
DC – Pulse length of
SyncSignals
DC – Latch0 Positive
Edge
DC – Latch0
Negative Edge
DC – Latch1 Positive
Edge
DC – Latch1
Negative Edge
DC – SyncManager
Event Times
General Purpose
Outputs [Byte]
General Purpose
Inputs [Byte]
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