Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manual de usuario descargar pdf (Pagina 25)

Features and Registers

Slave Controller – IP Core for Xilinx FPGAs III-13

Feature

IP Core

Xilinx

®

V2.04e

IP Core

Xilinx

V2.04d

Lost Link Counter

(0x0310:0x0313)

c

c

Watchdog

Watchdog Divider

configurable

(0x0400:0x0401)

c

c

Watchdog Process

Data

x

x

Watchdog PDI

x

x

Watchdog Counter

Process Data (0x0442)

x

x

Watchdog Counter PDI

(0x0443)

x

x

SII EEPROM Interface

(0x0500:0x050F)

EEPROM sizes

supported

1 KB-

4 Mbyte

1 KB-

4 Mbyte

EEPROM size

reflected in 0x0502.7

x

x

EEPROM controllable

by PDI

x

x

EEPROM Emulation by

PDI

c

c

Read data bytes

(0x0502.6)

4

4

Internal Pull-Ups for

EEPROM_CLK and

EEPROM_DATA

User logic

User logic

FMMUs

0-8

0-8

Bit-oriented operation

x

x

SyncManagers

0-8

0-8

Watchdog trigger

generation for 1 Byte

Mailbox configuration

independent of reading

access

x

x

SyncManager Event

Times (+0x8[7:6])

c

c

Buffer state (+0x5[7:6])

x

x

Distributed Clocks

c

c

Width

32/64

32/64

Sync/Latch signals

4

(2 Sync-

Signals, 2

Latch-

Signals)

4

(2 Sync-

Signals, 2

Latch-

Signals)

SyncManager Event

Times

(0x09F0:0x09FF)

c

c

DC Receive Times

c

c

DC Time Loop Control

controllable by PDI

c

c

DC activation by

EEPROM

(0x0140[11:10])

-

-

Propagation delay

measurement with

traffic (BWR/FPWR

0x900 detected at each

port)

x

x

LatchSignal state in

Latch Status register

(0x09AE:0x09AF)

x

x

SyncSignal Auto-

Activation (0x0981.3)

x

x

SyncSignal 32 or 64 bit

Start Time (0x0981.4)

x

x

SyncSignal Late

Activation

(0x0981[6:5])

x

x

SyncSignal debug

pulse (0x0981.7)

x

x

SyncSignal Activation

State 0x0984)

x

x

Reset filters after

writing filter depth

x

x

ESC Specific Registers

(0x0E00:0x0EFF)

Product and Vendor ID

x

x

POR Values

-

-

Feature

IP Core

Xilinx

®

V2.04e

IP Core

Xilinx

V2.04d

FPGA Update (online)

-

-

Process RAM and User RAM

Process RAM (0x1000

ff.) [KByte]

1-60

1-60

User RAM

(0x0F80:0x0FFF)

x

x

Extended ESC Feature

Availability in User

RAM

x

x

Additional EEPROMs

1-2

1-2

SII EEPROM (I²C)

c

(EEPROM

of µC

used)

c

(EEPROM

of µC

used)

FPGA configuration

EEPROM

x

x

LED Signals

RUN LED

c

c

RUN LED override

c

c

Link/Activity(x) LED per

port

x

x

PERR(x) LED per port

-

-

Device ERR LED

c

c

STATE_RUN LED

c

c

Optional LED states

RUN LED: Bootstrap

x

x

RUN LED: Booting

c

c

RUN LED: Device

identification

c

c

RUN LED: loading SII

EEPROM

c

c

Error LED: SII

EEPROM loading error

c

c

Error LED: Invalid

hardware configuration

-

-

Error LED: Process

data watchdog timeout

c

c

Error LED: PDI

watchdog timeout

c

c

Link/Activity: port

closed

-

-

Link/Activity: local auto-

negotiation error

-

-

Link/Activity: remote

auto-negotiation error

-

-

Link/Activity: unknown

PHY auto-negotiation

error

-

-

LED test

-

-

Clock supply

Crystal

-

-

Crystal oscillator

x

x

TX_CLK from PHY

x

x

25ppm clock source

accuracy

x

x

Internal PLL

User logic

User logic

Power Supply Voltages

FPGA

dep.

FPGA

dep.

I/O Voltage

FPGA

dep.

FPGA

dep.

Core Voltage

FPGA

dep.

FPGA

dep.

Internal LDOs

-

-

Package

FPGA

dep.

FPGA

dep.

Size [mm²]

FPGA

dep.

FPGA

dep.

Original Release date

1/2015

7/2013

Configuration and Pinout

calculator (XLS)

-

-

Register Configuration

individual

individual

Complete IP Core evaluation

x

x

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