Beckhoff EtherCAT IPCore Section III Manual de usuario descargar pdf (Pagina 3)

CONTENTS

Slave Controller – EtherCAT IP Core Data Sheet Addendum III

CONTENTS

1 Overview 1

2 EtherCAT IP Core for Altera FPGAs 1

2.1 FPGA design tool compatibility 1

2.2 FPGA device compatibility 3

2.3 FPGA device license support 4

2.4 Known Designflow Issues 5

2.4.1 General Quartus issues 5

2.4.1.1 Qsys: Avalon read error 5

2.4.2 Quartus 14 5

2.4.2.1 Quartus 14.1 Arria 10: Tristate drivers are not properly

connected 5

2.4.2.2 Quartus 14.0 and later: Cyclone III example designs are not

synthesizable 5

2.4.2.3 Quartus 14.0 with EtherCAT IP Core V3.0.0-V3.0.6: DE2-115

example designs are not working 5

3 EtherCAT IP Core for Xilinx FPGAs 6

3.1 FPGA design tool compatibility 6

3.2 FPGA device compatibility 7

3.3 Known Designflow Issues 8

3.3.1 General Vivado issues 8

3.3.1.1 Vivado Upgrade IP: Warning on port differences 8

3.3.1.2 The resource consumption of the EtherCAT IP Core is too high8

3.3.1.3 EtherCAT IP Core is not part of the IP Catalog 8

3.3.2 Vivado 2015 9

3.3.2.1 Vivado 2015.1: The resource consumption (Slice LUTs) of the

EtherCAT IP Core is too high 9

3.3.2.2 Vivado 2015.1: ZC702_AXI_VIVADO example design invalid

constraints 9

3.3.2.3 Vivado 2015.1: ZC702_AXI_VIVADO example design does not

meet timing requirements 9

3.3.2.4 Vivado 2015.1: ZC702_AXI_VIVADO example design and

EtherCAT IP cores outside the Zynq block design fails in SDK 9

3.3.3 Vivado 2014 10

3.3.3.1 Vivado 2014.4: ZC702_AXI_VIVADO example design and

EtherCAT IP cores outside the Zynq block design fails in SDK10

3.3.3.2 Vivado 2014.3: Abnormal program termination

(EXCEPTION_ACCESS_VIOLATION) 10

3.3.3.3 Vivado until 2014.3: Tri-state buffers inside EtherCAT IP Core10

3.3.3.4 Vivado until 2014.2: The resource consumption of the EtherCAT

IP Core is too high 10

3.3.3.5 Vivado until 2014.1: The ZC702 AXI Vivado example design is

not synthesizable 11

3.3.4 Vivado 2013 11

3.3.4.1 Vivado 2013.2 with EtherCAT IP Core until V3.00f: IP License

issue 11

3.3.5 ISE/EDK/PlanAhead 14.7 12

3.3.5.1 ISE: Crash in libSecurity_FNP.dll 12

3.3.5.2 ISE/EDK/PlanAhead: Additional BUFG inserted 12

3.3.5.3 ISE/EDK/PlanAhead: CLOCK_DEDICATED_ROUTE=FALSE

constraint required 12

4 Appendix 13

4.1 Support and Service 13

4.1.1 Beckhoff’s branch offices and representatives 13

4.2 Beckhoff Headquarters 13

1 2 3 4 5 6 7 8 ... 15 16

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